S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0F7, 0x1F7, 0x2F7, 0x3F7, 0x4F7, 0x5F7, 0x6F7, 0x7F7:
RASE Receive Z1/S1
Bit
Type
R
R
R
R
R
R
R
R
Function
Z1/S1[7]
Z1/S1[6]
Z1/S1[5]
Z1/S1[4]
Z1/S1[3]
Z1/S1[2]
Z1/S1[1]
Z1/S1[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Z1/S1[3:0]:
The lower nibble of the first Z1/S1 byte contained in the receive stream is extracted into this
register. The Z1/S1 byte is used to carry synchronization status messages between line
terminating network elements. Z1/S1[3] is the most significant bit corresponding to bit 5,
the first bit received. Z1/S1[0] is the least significant bit, corresponding to bit 8, the last bit
received. An interrupt may be generated when a byte value is received that differs from the
value extracted in the previous frame (using the Z1/S1E bit in the RASE Interrupt Enable
Register). In addition, debouncing can be performed where the register is not loaded until
eight of the same consecutive nibbles are received. Debouncing is controlled using the
Z1/S1_CAP bit in the RASE Configuration/Control register.
Z1/S1[7:4]:
The upper nibble of the first Z1/S1 byte contained in the receive stream is extracted into this
register. No interrupt is asserted on the change of this nibble. In addition, when the
Z1/S1_CAP bit in the RASE Configuration/Control register selects debouncing, the upper
nibble is only updated when eight of the same consecutive lower nibbles are received.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
298
PMC [ PMC-SIERRA, INC ]
