S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0FF, 0x1FF, 0x2FF, 0x3FF, 0x4FF, 0x5FF, 0x6FF, 0x7FF:
Channel Clock Monitors
Bit
Type
Function
Unused
Unused
Unused
Unused
RCLKA
TCLKA
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
R
R
R
R
RFCLKA
TFCLKA
This register provides activity monitoring of the channel clocks. When a monitored clock signal
makes a low to high transition, the corresponding register bit is set high. The bit will remain
high until this register is read, at which point, all the bits in this register are cleared. A lack of
transitions is indicated by the corresponding register bit reading low. This register should be
read at periodic intervals to detect clock failures.
TFCLKA:
The TFCLK active (TFCLKA) bit monitors for low to high transition on the channel’s
TFCLK internal clock. TFCLKA is set high on a rising edge of Level 2 TFCLK and is set
low when this register is read.
RFCLKA:
The RFCLK active (RFCLKA) bit monitors for low to high transition on the channel’s
RFCLK internal clock. RFCLKA is set high on a rising edge of Level 2 RFCLK and is set
low when this register is read.
RCLKA:
The RCLK active (RCLKA) bit monitors for low to high transition on the channel’s RCLK
receive line rate clock. RCLKA is set high on a rising edge of channel RCLK and is set low
when this register is read.
TCLKA:
The TCLK active (TCLKA) bit monitors for low to high transition on the channel’s TCLK
transmit line rate clock. TCLKA is set high on a rising edge of TCLK and is set low when
this register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
302
PMC [ PMC-SIERRA, INC ]
