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PM5380-BI 参数 Datasheet PDF下载

PM5380-BI图片预览
型号: PM5380-BI
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC,]
分类和应用:
文件页数/大小: 440 页 / 2124 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM5380-BI的Datasheet PDF文件第292页浏览型号PM5380-BI的Datasheet PDF文件第293页浏览型号PM5380-BI的Datasheet PDF文件第294页浏览型号PM5380-BI的Datasheet PDF文件第295页浏览型号PM5380-BI的Datasheet PDF文件第297页浏览型号PM5380-BI的Datasheet PDF文件第298页浏览型号PM5380-BI的Datasheet PDF文件第299页浏览型号PM5380-BI的Datasheet PDF文件第300页  
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet  
Released  
Register 0x0F5, 0x1F5, 0x2F5, 0x3F5, 0x4F5, 0x5F5, 0x6F5, 0x7F5:  
RASE Receive K1  
Bit  
Type  
Function  
K1[7]  
K1[6]  
K1[5]  
K1[4]  
K1[3]  
K1[2]  
K1[1]  
K1[0]  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R
R
R
R
R
R
R
R
X
X
X
X
X
X
X
X
K1[7:0]:  
The K1[7:0] bits contain the current K1 code value. The contents of this register are  
updated when a new K1 code value (different from the current K1 code value) has been  
received for three consecutive frames. An interrupt may be generated when a new code  
value is received (using the COAPSE bit in the RASE Interrupt Enable Register). K1[7] is  
the most significant bit corresponding to bit 1, the first bit received. K1[0] is the least  
significant bit, corresponding to bit 8, the last bit received.  
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC- 2010299, Issue 2  
296  
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