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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
SBI bus. This is selected when the SYSOPT[2:0] bits in the Global Configuration  
register are set to “SBI Interface with CAS or CCS H-MVIP Interface” and the  
ICCSSEL bit in the T1/E1 Ingress Serial Interface Mode Select register is set to  
0.  
A separate H-MVIP interface consisting of a single signal is used to time division  
multiplex the common channel signaling (CCS) for all T1s and E1s and  
additionally the V5 channels in E1 mode. The CCS H-MVIP interface, CCSID, is  
not multiplexed with any other pins. CCSID can be used in parallel with the Clock  
Slave:H-MVIP mode when SYSOPT[2:0] is set to “H-MVIP Interface” and the  
ICCSSEL bit in the T1/E1 Ingress Serial Interface Mode Select register is set to  
1, a Clock Slave serial interface when SYSOPT[2:0] is set to “Serial Clock and  
Data Interface with CCS H-MVIP Interface”, or the SBI Add bus when  
SYSOPT[2:0] is set to “SBI Interface with CAS or CCS H-MVIP Interface” and  
the ICCSSEL bit is set to 1.  
When accessing the CAS or CCS signaling via the H-MVIP interface in parallel  
with serial clock and data or SBI interfaces a receive signaling elastic store is  
used to adapt any timing differences between the data interface and the CAS or  
CCS H-MVIP interface.  
Figure 26: Clock Slave: Serial Data and H-MVIP CCS  
ID[1:28]  
IFP[1:28]  
RECEIVER  
ICLK[1:28]  
Outputs Timed  
to ICLK[x]  
ELST  
Elastic  
Store  
FRAM  
Framer:  
Slip Buffer RAM  
ISIF  
Ingress  
System  
Interface  
CCSID  
CMVFP  
CMVFPC  
RJAT  
Receive Data[1:28]  
Receive CLK[1:28]  
FRMR  
Digital Jitter  
Attenuator  
Framer:  
Frame Alignment,  
Alarm Extraction  
CMV8MCLK  
Inputs Timed  
to CMV8MCLK  
When Clock Slave: H-MVIP mode is enabled, payload data may be extracted  
throught the ingress serial interface, while common channel signaling is  
extracted in parallel through the H-MVIP interface.  
The H-MVIP ingress interface multiplexes common channel signalling from up to  
28 T1s or 21 E1s. The H-MVIP interfaces use common clocks, CMV8MCLK and  
CMVFPC, and frame pulse, CMVFPB, for synchronization. Common channel  
signaling over H-MVIP uses a Clock Slave serial interface, selected when  
PROPRIETARY AND CONFIDENTIAL  
95  
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