STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
SYSOPT[2:0] is set to “Serial Clock and Data Interface with CCS H-MVIP
Interface”. CCSID is a singal dedicated output pin, output relative to
CMV8MCLK, used to time division multiplex the common channel signaling
(CCS) for all T1s and E1s, and additionally the V5 channels in E1 mode.
The ingress clock, ICLK[x], is a 1.544MHz or 2.048MHz clock generated from the
16.384MHz CMV8MCLK. (Note that in T1 mode, this clock does not divide down
to T1 rate evenly, resulting in a gappy clock. The minimum period is 10 times
that of CMV8MCLK.) ICLK[x] is pulsed for each bit in the 193 bit T1 or 256 bit
E1 frame (i.e. NxDS0 controls are not applicable in this mode). Payload data on
ED[x] is sampled by this clock. The egress frame alignment is indicated by
TECT3 on EFP[x], again timed to ICLK[x].
Note that several of the serial PMC ingress data pins ID[x] are multiplexed with
the ingress data H-MVIP interface. ID[1,5,9,13,17,21,25] share pins with the H-
MVIP data signals MVID[1:7]. ID[2,6,10,14,18,22,26] share pins with the H-MVIP
CAS signals CASID[1:7]. Note also that in this mode, a receive signaling elastic
store is used to adapt any timing differences between the data interface and the
CCS H-MVIP interface.
9.30 Extract Scaleable Bandwidth Interconnect (EXSBI)
The Extract Scaleable Bandwidth Interconnect block demaps up to 28 1.544Mb/s
links or a single 44.736Mb/s link from the SBI shared bus. The 1.544Mb/s links
can be unframed when used in a straight multiplexer application, or they can be
T1 framed and channelized for insertion into the DS3 multiplex. The 44.736Mb/s
link can be DS3 unchannelized when the TECT3 is used as a DS3 framer.
All egress links extracted from the SBI bus can be timed from the source or from
the TECT3. When Timing is from the source the EXSBI commands the PISO to
generate 1.544Mb/s or 44.736Mb/s clocks slaved to the arrival rate of the data or
from timing link rate adjustments provided from the source and carried with the
links over the SBI bus. The 1.544Mb/s clock is synthesized from the 19.44MHz
reference clock, SREFCLK, by dividing the clock by either 12 or 13 in a fixed
sequence that produces the nominal 1.544Mb/s rate. Timing adjustments are
made over 500uS intervals and are done by either advancing or retarding the
phase or by adding or deleting a whole 1.544Mb/s clock cycle over the 500uS
period.
The 44.736Mb/s clock is synthesized from the 51.84MHz or 44.928MHz
reference clock, CLK52M. Using either reference clock frequency, the
44.736Mb/s rate is generated by gapping the reference clock in a fixed way.
Timing adjustments are performed by adding or deleting four clocks over the
500uS period.
PROPRIETARY AND CONFIDENTIAL
96
PMC [ PMC-SIERRA, INC ]
