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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
Figure 21: Clock Master: Full T1/E1  
RECEIVER  
FRAM  
ID[1:28]  
Framer:  
ISIF  
Slip Buffer RAM  
IFP[1:28]  
Ingress  
System  
Interface  
RJAT  
Receive Data[1:28]  
Receive CLK[1:28]  
FRMR  
ID[x], IFP[x]  
Timed to  
ICLK[1:28]  
Digital Jitter  
Attenuator  
Framer:  
Frame Alignment,  
Alarm Extraction  
ICLK[1:28]  
In Clock Master: Full T1/E1 mode, the elastic store is bypassed and the ingress  
clock (ICLK[x]) is a jitter attenuated version of the 1.544 MHz or 2.048 MHz  
receive clock coming from the M13 multiplex. Jitter attenuation is selectable by  
the RJATBYP bit in the T1/E1 Receive Options register. ICLK[x] is pulsed for  
each bit in the 193 bit T1 or 256 bit E1 frame. The ingress data appears on ID[x]  
and the ingress frame alignment is indicated by IFP[x]. In this mode,  
demultiplexed T1 or E1 data passes through the TECT3 unchanged during out-  
of-frame conditions, similar to an offline framer system. When the TECT3 is the  
clock master in the ingress direction, the elastic store is used to buffer between  
the ingress and egress clocks to facilitate per-Channel loopback.  
Figure 22: Clock Master: NxChannel  
RECEIVER  
FRAM  
Framer:  
ID[1:28]  
IFP[1:28]  
ISIF  
Slip Buffer RAM  
Ingress  
System  
Interface  
RJAT  
Receive Data[1:28]  
Receive CLK[1:28]  
FRMR  
ICLK[1:28]  
Digital Jitter  
Attenuator  
Framer:  
Frame Alignment,  
Alarm Extraction  
ID[x], IFP[x]  
Timed to  
gapped  
ICLK[1:28]  
In Clock Master: NxChannel mode, ICLK[x] is a gapped version of the jitter  
attenuated 1.544 MHz or 2.048 MHz receive clock coming from the M13  
multiplex. ICLK[x] is gapped on a per channel basis so that a subset of the 24  
channels in the T1 frame or 32 channels in an E1 frame is extracted on ID[x].  
IFP[x] indicates frame alignment but has no clock since it is gapped during the  
framing bits. Channel extraction is controlled by the RPSC block. The framing bit  
position is always gapped, so the number of ICLK[x] pulses is controllable from 0  
to 192 pulses per T1 frame or 0 to 256 pulses per E1 frame on a per-channel  
basis. In this mode, demultiplexed or demapped T1 or E1 streams pass through  
PROPRIETARY AND CONFIDENTIAL  
92  
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