STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
9.32 Scaleable Bandwidth Interconnect PISO (SBIPISO)
The Scaleable Bandwidth Interconnect Parallel to Serial converter (SBIPISO)
generates up to 28 T1s or a DS3 serial clock and data signals from the byte
serial stream provided by the Extract SBI block. The generated clock rate can be
controlled with commands from the EXSBI. In clock slave mode the generated
clock will be increased or decreased in small increments based on FIFO fill levels
within the EXSBI or directly with clock rate commands from the far end device
who is mastering the clock across the SBI bus. In clock master mode the
SBIPISO controls the bit rate by accepting data from the EXSBI at the rate of the
individual T1 or DS3 clocks sourced into it.
In addition the SBIPISO generates serial CAS signaling streams, frame pulses
and multiframe pulses for all T1s and DS3.
9.33 Scaleable Bandwidth Interconnect SIPO (SBISIPO)
The Scaleable Bandwidth Interconnect Serial to Parallel converter (SBISIPO)
sinks up to 28 T1s or a DS3 serial clock and data signals and generates a byte
serial stream to the Insert SBI block. The SBISIPO measures the serial clock
against the SBI reference clock and sends this information to the INSBI block
and in turn across the SBI bus to the clock generation slave, SBIPISO. In this
way an accurate representation of the input clock rate is communicated across
the SBI bus.
In addition the SBISIPO generates byte serial streams from serial CAS signaling
signals, frame pulses and multiframe pulses for all T1s and DS3.
9.34 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan.
The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST
instructions are supported. The TECT3 identification code is 383150CD
hexadecimal.
9.35 Microprocessor Interface
The Microprocessor Interface Block provides normal and test mode registers, the
interrupt logic, and the logic required to connect to the Microprocessor Interface.
The normal mode registers are required for normal operation, and test mode
registers are used to enhance the testability of the TECT3.
The Register Memory Map in Table 2 shows where the normal mode registers
are accessed. The registers are organized so that backward software
PROPRIETARY AND CONFIDENTIAL
98
PMC [ PMC-SIERRA, INC ]
