STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 25: Clock Slave: H-MVIP
RECEIVER
ELST
Elastic
FRAM
Framer:
Store
MVID[1:7]
Slip Buffer RAM
CASID [1:7]
ISIF
Ingress
Syst em
Interface
CCSID
RJAT
Receive Data[1:28]
Receive CLK[1:28]
FRMR
Digita l Jitter
Attenuator
Framer:
CMVFP
Frame A lignmen t,
Alarm Ext raction
CMVFPC
CMV8MCLK
Inputs Time d
to CMV8MC LK
When Clock Slave: H-MVIP mode is enabled a 8.192Mb/s H-MVIP ingress
interface multiplexes up to 672 channels from 28 T1s or 21 E1s, up to 672
channel associated signaling (CAS) channels from 28 T1s or 21 E1s and
common channel signaling (CCS) from up to 28 T1s or 21 E1s. The H-MVIP
interfaces use common clocks, CMV8MCLK and CMVFPC, and frame pulse,
CMVFPB, for synchronization.
The three ingress H-MVIP interfaces operate independently except that using
any one of these forces the T1 or E1 framer to operate in synchronous mode,
meaning that elastic stores are used.
Seven H-MVIP data signals, MVID[1:7], share pins with serial PCM data outputs,
ID[x], to provide H-MVIP access for up to 672 data channels. The H-MVIP
mapping is fixed such that each group of four nearest neighbor T1 or E1 links
make up the individual 8.192Mb/s H-MVIP signal. The multiplexed data input is
shared with the lowest numbered T1 or E1 serial PCM link in the bundle, for
example MViD[2] combines the DS0s or timeslots of ID[5,6,7,8] and is pin
multiplexed with ID[5]. This mode is selected when the SYSOPT[2:0] bits in the
Global Configuration register are set to H-MVIP.
A separate H-MVIP interface consisting of seven pins is for access to the
channel associated signaling for all of the 672 data channels. The CAS is time
division multiplexed exactly the same way as the data channels and is
synchronized with the H-MVIP data channels. Over a T1 or E1 multi-frame the
four CAS bits per channel are repeated with each data byte. Four stuff bits are
used to pad each CAS nibble (ABCD bits) out to a full byte in synchronization
with each data byte. The ingress CAS H-MVIP interface, CASID[1:7], is
multiplexed with seven serial PCM ingress data pins, ID[2,6,10,14,18,22,26].
The CAS H-MVIP interface can be used in parallel with the SBI Drop bus as an
alternative method for accessing the CAS bits while data transfer occurs over the
PROPRIETARY AND CONFIDENTIAL
94
PMC [ PMC-SIERRA, INC ]
