STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
and E1s and additionally the V5 channels in E1 mode. The V5 channels in E1
mode can also be enabled over CCSED when the ETS15EN and ETS31EN bits
in the T1/E1 Egress Serial Interface Mode Select register are set to 1.
The ingress clock, ICLK[x], is a 1.544MHz or 2.048MHz clock generated from the
16.384MHz CMV8MCLK. (Note that in T1 mode, this clock does not divide down
to T1 rate evenly, resulting in a gappy clock. The minimum period is 10 times
that of CMV8MCLK.) ICLK[x] is pulsed for each bit in the 193 bit T1 or 256 bit
E1 frame (i.e. NxDS0 controls are not applicable in this mode). Payload data on
ID[x] is output relative to this clock. The ingress frame alignment is indicated by
TECT3 on IFP[x], again timed to ICLK[x].
Note that several of the serial PCM egress data pins ED[x] are multiplexed with
the egress data H-MVIP data interface. ED[1,5,9,13,17,21,25] share pins with
the H-MVIP data signals MVED[1:7]. ED[2,6,10,14,18,22,26] share pins with the
H-MVIP CAS signals CASED[1:7].
9.29 Ingress System Interface (ISIF)
The Ingress System Interface (ISIF) block provides system side serial clock and
data access as well as H-MVIP access for up to 28 T1 or 21 E1 receive streams.
There are several master and slave clock modes for serial clock and data system
side access to the T1 and E1 streams. When enabled for 8.192Mb/s H-MVIP
there are three separate interfaces for data and signaling. The H-MVIP signaling
interfaces can be used in combination with the serial clock and data and SBI
interface in certain applications. Control of the system side interface is global to
TECT3 and is selected through the SYSOPT[2:0] bits in the Global Configuration
register at address 0001H. The system interface options are serial clock and
data, H-MVIP, SBI bus, SBI bus with CAS or CCS H-MVIP and serial clock and
data with CCS H-MVIP.
Three Clock Master modes provide a serial clock and data ingress interface with
clocking provided by TECT3. The clock master modes are Clock Master: Full
T1/E1, Clock Master : NxChannel, Clock Master: Clear Channel. Two Clock
slave modes provide two serial clock and data ingress interfaces and a H-MVIP
interface. All Clock slave modes accept externally sourced clocking. The clock
slave modes are: Clock Slave: External Signaling or Clock Slave: H-MVIP. The
ingress serial clock and data interface clocking modes are selected via the
IMODE[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register. Clock
Master: NxChannel and Clock Master: Full T1/E1 use the same IMODE[1:0]
selection and are differentiated by the INXCHAN[1:0] bits in the same ragister as
IMODE[1:0].
PROPRIETARY AND CONFIDENTIAL
91
PMC [ PMC-SIERRA, INC ]
