STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
the TECT3 unchanged during out-of-frame conditions. The parity functions are
not usable in NxChannel mode. When the TECT3 is the clock master in the
ingress direction, the elastic store is used to buffer between the ingress and
egress clocks to facilitate per-Channel loopback.
Figure 23: Clock Master: Clear Channel
RECEIVER
ID[x]Timed to
ICLK[x]
ISIF
Ingress
ID[1:28]
System
RJAT
Receive Data[1:28]
Receive CLK[1:28]
Interfac e
Digita l Jitter
Attenuator
ICLK[ 1:28]
In Clock Master: Clear Channel mode, the elastic store is bypassed and the
ingress clock (ICLK[x]) is a jitter attenuated version of the 1.544 MHz or 2.048
MHz receive clock coming from the M13 multiplex. The ingress data appears on
ID[x] which no frame alignment indication. Per channel loopbacks are not
available in Clear channel mode. The RCVCLRCH mode bit in the T1/E1
Receive Options register must be set to 1 in Clock master: Clear Channel mode.
Figure 24: Clock Slave: External Signaling
CICLK
ELST
Elastic
RECEIVER
CIFP
FRAM
Framer:
Store
Slip Buffer RAM
ID[1:28]
IFP[1:28]
ISIG[1:28]
RJAT
Receive Data[1:28]
Receive CLK[1:28]
ISIF
FRMR
Digital Jitter
Attenuator
Ingress
System
Interface
Framer:
Frame Alignment,
Alarm Extraction
ID[x], IFP[x],
ISIG[x]
Timed to CICLK
In Clock Slave: External Signaling mode, the elastic store is enabled to permit
CICLK to specify the ingress-side timing. The ingress data on ID[x] and signaling
ISIG[x] are bit aligned to the 1.544 MHz or 2.048 MHz common ingress clock
(CICLK) and are frame aligned to the common ingress frame pulse (CIFP).
CICLK can be enabled to be a 1.544 MHz clock or a 2.048 MHz clock. ISIG[x]
contains the robbed-bit signaling state (ABCD or ABAB) in the lower four bits of
each channel. IFP[x] indicates either the frame or superframe alignment on ID[x].
PROPRIETARY AND CONFIDENTIAL
93
PMC [ PMC-SIERRA, INC ]
