欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM4328-PI的Datasheet PDF文件第99页浏览型号PM4328-PI的Datasheet PDF文件第100页浏览型号PM4328-PI的Datasheet PDF文件第101页浏览型号PM4328-PI的Datasheet PDF文件第102页浏览型号PM4328-PI的Datasheet PDF文件第104页浏览型号PM4328-PI的Datasheet PDF文件第105页浏览型号PM4328-PI的Datasheet PDF文件第106页浏览型号PM4328-PI的Datasheet PDF文件第107页  
STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
A separate H-MVIP interface consisting of a single signal is used to time division  
multiplex the common channel signaling (CCS) for all T1s and E1s and  
additionally the V5 channels in E1 mode. The CCS H-MVIP interface, CCSED, is  
not multiplexed with any other pins. CCSED can be used in parallel with the  
Clock Slave:H-MVIP mode when SYSOPT[2:0] is set to “H-MVIP Interface” and  
the ECCSEN bit in the T1/E1 Egress Serial Interface Mode Select register is set  
to 1, a Clock Slave serial interface when SYSOPT[2:0] is set to “Serial Clock and  
Data Interface with CCS H-MVIP Interface”, or the SBI Add bus when  
SYSOPT[2:0] is set to “SBI Interface with CAS or CCS H-MVIP Interface” and  
the ECCSEN bit is set to 1. The V5 channels in E1 mode can also be enabled  
over CCSEN when the ETS15EN and ETS31EN bits in the T1/E1 Egress Serial  
Interface Mode Select register are set to 1.  
When accessing the CAS or CCS signaling via the H-MVIP interface in parallel  
with the SBI interface a transmit signaling elastic store is used to adapt any  
timing differences between the data interface and the CAS or CCS H-MVIP  
interface.  
Figure 20: Clock Master: Serial Data and H-MVIP CCS  
TRANSMITTER  
ED[1:28]  
EFP[1:28]  
ICLK[1:28]  
ED[x] Inputs  
Timed to  
ICLK[x]  
T1-XBAS/E1-TRAN  
TJAT  
ESIF  
Egress  
System  
Interface  
BasicTransmitter:  
Frame Generation,  
Alarm Insertion,  
Signaling Insertion,  
Trunk Conditioning  
Line Coding  
Transmit CLK[1:28]  
Transmit Data[1:28]  
Digital PLL  
CCSED  
CMVFP  
CMVFPC  
TJAT  
FIFO  
CMV8MCLK  
Inputs Timed  
to CMV8MCLK  
When Clock Master: Serial Data and H-MVIP CCS mode is enabled, payload  
data may be sourced through the egress serial interface, while common channel  
signaling is sourced in parallel through the H-MVIP interface.  
The H-MVIP egress interface multiplexes common channel signaling from up to  
28 T1s or 21 E1s. The H-MVIP interfaces use common clocks, CMV8MCLK and  
CMVFPC, and frame pulse, CMVFPB, for synchronization. Common channel  
signaling over H-MVIP uses a Clock Slave serial interface, selected when  
SYSOPT[2:0] is set to “Serial Clock and Data Interface with CCS H-MVIP  
Interface”. CCSED is a single dedicated input pin sampled by CMV8MCLK,  
used to time division multiplex the common channel signaling (CCS) for all T1s  
PROPRIETARY AND CONFIDENTIAL  
90  
 复制成功!