STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 17: Clock Slave: External Signaling
TRANSMITTER
T1-XBAS/E1-TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
ED[1:28]
TJAT
ESIF
Egress
System
Interface
Transmit CLK[1:28]
Transmit Data[1:28]
Digital PLL
ESIG[1:28]
TJAT
Signaling Insertion,
Trunk Conditioning
Line Coding
CEFP
CECLK
FIFO
Inputs Timed
to CECLK
In Clock Slave: External Signaling mode, the egress interface is clocked by the
common egress clock, CECLK. The transmitter is either frame-aligned or
superframe-aligned to the common egress frame pulse, CEFP, via the CEMFP
bit in the Master Egress Slave Mode Serial Interface Configuration register. The
ESIG[x] signal contains the robbed-bit signaling data to be inserted into Transmit
Data[x], with the four least significant bits of each channel on ESIG[x]
representing the signaling state (ABCD or ABAB in T1 SF mode). EFP[x] is not
available in this mode.
Figure 18: Clock Slave: Clear Channel
TRANSMITTER
ED[1:28]
TJAT
ESIF
Egress
System
Interface
Transmit CLK[1:28]
Transmit Data[1:28]
Digital PLL
TJAT
FIFO
ECLK[1:28]
Input Timed
to ECLK[x]
In Clock Slave: Clear Channel mode, the egress interface is clocked by the
externally provided egress clock, ECLK[x]. ECLK[x] must be a 1.544 MHz clock
for T1 links or a 2.048 MHz clock for E1 links. In this mode the T1/E1 framers are
bypassed except for the TJAT which may or may not be bypassed depending on
the setting of the TJATBYP bit in the T1/E1 Egress Line Interface Options
register. Typically the TJAT would be bypassed unless jitter attenuation is
required on ECLK[x].
PROPRIETARY AND CONFIDENTIAL
88
PMC [ PMC-SIERRA, INC ]
