STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Figure 15: Clock Master: Clear Channel
CTCLK
Receive CLK[1:28]
ED[1:28]
TJAT
ESIF
Transmit CLK[1:28]
Transmit Data[1:28]
Digital PLL
ECLK[1:28]
Egress
System
Interface
ED[x] Timed
to ECLK[x]
TRANSMITTER
Clock Master: Clear Channel mode has no frame alignment therefore no frame
alignment is indicated to the upstream device. ECLK[x] is a continuous clock at
1.544Mb/s for T1 links or 2.048Mb/s for E1 links.
Figure 16: Clock Slave: EFP Enabled
TRANSMITTER
T1-XBAS/E1-TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
ED[1:28]
TJAT
ESIF
Egress
System
Interface
Digital PLL
Transmit CLK[1:28]
Transmit Data[1:28]
EFP[1:28]
TJAT
Signaling Insertion,
Trunk Conditioning
Line Coding
CEFP
CECLK
FIFO
Inputs Timed
to CECLK
In Clock Slave: EFP Enabled mode, the egress interface is clocked by the
common egress clock, CECLK. The transmitter is either frame-aligned or
superframe-aligned to the common egress frame pulse, CEFP, via the CEMFP
bit in the Master Egress Slave Mode Serial Interface Configuration register.
EFP[x] is configurable to indicate the frame alignment or the superframe
alignment of ED[x]. CECLK can be enabled to be either a 1.544 MHz clock for
T1 links or a 2.048 MHz clock for T1 and E1 links. The CECLK2M bit in the
Master Egress Slave Mode Serial Interface Configuration register selects the
2.048MHz clock for T1 operation.
PROPRIETARY AND CONFIDENTIAL
87
PMC [ PMC-SIERRA, INC ]
