STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
NxChannel and Clock Master: Clear Channel. Four Clock slave modes provide
three serial clock and data egress interfaces and a H-MVIP interface all with
externally sourced clocking. The slave modes are Clock Slave: EFP Enabled,
Clock Slave: External Signaling, Clock Slave: Clear Channel and Clock Slave: H-
MVIP. The egress serial clock and data interface clocking modes are selected via
the EMODE[2:0] bits in the T1/E1 Egress Serial Interface Mode Select register.
In all egress Clock Master modes the transmit clock can be sourced from either
the common transmit clock, CTCLK, one of the two recovered clocks,
RECVCLK1 and RECVCLK2, or the received clock for that link. The selection
between CTCLK, RECVCLK1 and RECVCLK2 as the reference transmit clock is
the same for all T1/E1 framers. Jitter attenuation can be applied to all master
mode clocks with the TJAT.
Figure 14: Clock Master: NxChannel
CTCLK
Receive CLK[1:28]
T1-XBAS/E1-TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
ED[1:28]
TJAT
ESIF
Egress
System
Interface
Transmit CLK[1:28]
Transmit Data[1:28]
Digital PLL
ECLK[1:28]
Signaling Insertion,
Trunk Conditioning
Line Coding
ED[x] Timed
to ECLK[x]
TRANSMITTER
Clock Master: NxChannel mode does not indicate frame alignment to the
upstream device. Instead, ECLK[x] is gapped on a per channel basis so that a
subset of the 24 channels in a T1 frame or 32 channels in an E1 frame are
inserted on ED[x]. Channel insertion is controlled by the IDLE_CHAN bits in the
TPSC block’s Egress Control Bytes. The framing bit position is always gapped,
so the number of ECLK[x] pulses is controllable from 0 to 192 pulses per T1
frame or 0 to 256 pulses per E1 frame on a per-channel basis. The parity
functions should not be enabled in NxChannel mode.
PROPRIETARY AND CONFIDENTIAL
86
PMC [ PMC-SIERRA, INC ]
