STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
mode. When an OOF occurs, the FERF value is held at the state contained in
the last buffer location corresponding to the previous sixth M-frame or G.747
frame. This location is not updated until the OOF condition is deasserted.
Meanwhile, the last four of the remaining five buffer locations are loaded with the
frozen FERF state while the first buffer location corresponding to the current M-
frame/ G.747 frame is continually updated every M-frame/G.747 frame based on
the above FERF definition. Once correct frame alignment has been found and
OOF is deasserted, the first buffer location will contain a valid FERF status and
the remaining five buffer locations are enabled to be updated every M-frame or
G.747 frame.
DS2 M-bit and F-bit framing errors are indicated as are G.747 framing word
errors (or bit errors) and G.747 parity errors. These error indications are
accumulated for performance monitoring purposes in internal, microprocessor
readable counters. The performance monitoring accumulators continue to count
error indication even while the framer is indicating OOF.
The DS2 FRMR may be configured to generate interrupts on error events or
status changes. All sources of interrupts can be masked or acknowledged via
internal registers. Internal registers are also used to configure the DS2 FRMR.
9.27 M12 Multiplexer (MX12)
The MX12 M12 Multiplexer integrates circuitry required to asynchronously
multiplex and demultiplex four DS1 streams into, and out of, an M12 formatted
DS2 serial stream (as defined in ANSI T1.107 Section 7) and to support
asynchronous multiplexing and demultiplexing of three 2048 kbit/s into and out of
a G.747 formatted 6312 kbit/s high speed signal (as defined in CCITT Rec.
G.747).
When multiplexing four DS1 streams into an M12 formatted DS2 stream, the
MX12 TSB performs logical inversion on the second and fourth tributary streams.
Rate adaptation to the DS2 is performed by integral FIFO buffers, controlled by
timing circuitry. The FIFO buffers accommodate in excess of 5.0 UIpp of
sinusoidal jitter on the DS1 clocks for all jitter frequencies. X, F, M, and C bits
are also generated and inserted by the timing circuitry. Software control is
provided to transmit Far End Receive Failure (FERF) indications, DS2 AIS, and
DS1 payload loopback requests. The loopback request is coded by inverting one
of the three C-bits (the default option is compatible with ANSI T1.107a Section
8.2.1 and TR-TSY-000009 Section 3.7).Two diagnostic options are provided to
invert the transmitted F or M bits.
When demultiplexing four DS1 streams from an M12 formatted DS2, the MX12
performs bit destuffing via interpretation of the C-bits. The MX12 also detects
and indicates DS1 payload loopback requests encoded in the C-bits. As per
PROPRIETARY AND CONFIDENTIAL
84
PMC [ PMC-SIERRA, INC ]
