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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
ANSI T1.107 Section 7.2.1.1 and TR-TSY-000009 Section 3.7, the loopback  
command is identified as C3 being the inverse of C1 and C2. Because TR-TSY-  
000233 Section 5.3.14.1 recommends compatibility with non-compliant existing  
equipment, the two other loopback command possibilities are also supported. As  
per TR-TSY-000009 Section 3.7, the loopback request must be present for five  
successive M-frames before declaration of detection. Removal of the loopback  
request is declared when it has been absent for five successive M-frames.  
DS1 payload loopback can be activated or deactivated under software control.  
During payload loopback the DS1 stream being looped back still continues  
unaffected in the demultiplex direction. The second and fourth demultiplexed  
DS1 streams are logically inverted, and all four demultiplexed DS1 streams can  
be replaced with AIS on an individual basis.  
Similar functionality supports CCITT Recommendation G.747. The FIFO is still  
required for rate adaptation. The frame alignment signal and parity bit are  
generated and inserted by the timing circuitry. Software control is provided to  
transmit Remote Alarm Indication (RAI), high speed signal AIS, and the reserved  
bit. A diagnostic option is provided to invert the transmitted frame alignment  
signal and parity bit.  
When demultiplexing three 2048 kbit/s streams from a G.747 formatted 6312  
kbit/s stream, the MX12 performs bit destuffing via interpretation of the C-bits.  
Tributary payload loopback can be activated or deactivated under software  
control. Although no remote loopback request has been defined for G.747,  
inversion of the third C-bit triggers a loopback request detection indication in  
anticipation of Recommendation G.747 refinement. All three demultiplexed 2048  
kbit/s streams can be replaced with AIS on an individual basis.  
9.28 Egress System Interface (ESIF)  
The Egress System Interface (ESIF) block provides system side serial clock and  
data access as well as H-MVIP access for up to 28 T1 or 21 E1 transmit  
streams. There are several master and slave clocking modes for serial clock and  
data system side access to the T1 and E1 streams. When enabled for 8.192Mb/s  
H-MVIP there are three separate interfaces for data, CAS signaling and CCS  
signaling. The H-MVIP signaling interfaces can be used in combination with the  
serial clock and data and SBI interface in certain applications. Control of the  
system side interface is global to TECT3 and is selected through the  
SYSOPT[2:0] bits in the Global Configuration register at address 0001H. The  
system interface options are serial clock and data, H-MVIP, SBI bus, SBI bus  
with CAS or CCS H-MVIP and serial clock and data with CCS H-MVIP.  
Two Clock Master modes provide a serial clock and data egress interface with  
per link clocking provided by TECT3. The clock master modes are Clock Master:  
PROPRIETARY AND CONFIDENTIAL  
85  
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