TransDimension Inc.
Interfacing TD242LP to Intel StrongArm SA1110 Processor
Alternative clock input for the LQFP64
6MHz is the only crystal oscillator frequency supported. However, the LQFP64 supports three
alternative clock inputs. First is a single-ended 6MHz oscillator, with a 2.5V output, connected to
OSC1. OSC2 and CLKW must be tied to ground. Second is a single-ended 48MHz oscillator,
also with a 2.5V output, connected to OSC2. OSC1 must be tied to 3.3V and CLKW must be tied
to ground. Third is a single-ended 6MHz or 48MHz oscillator, with a 3.3V output, connected to
CLKW. OSC1 must be tied to 3.3V and OSC2 must be tied to ground. Coming out of RESET,
the VBP pin is sampled to determine the frequency used per the table below. The TD242LP does
not distinguish between a crystal and a single-ended oscillator. Do not use this table for the
BGA64 package.
VBP
6MHz
48MHz
0
1
Figure 9: Frequency Selection for the LQFP64 package
2.3 Software Configuration
Bus Cycle Timing
Bus cycle timing parameters for the TD242LP read/write operation are listed below. The
TD242LP memory/register read and write cycles are illustrated in Figures 11 and 12,
respectively.
Symbol
tRPW
tWPW
tACR
tASL
tAHH
tDSW
tDVR
tDHR
Parameter
Min
55
55
25
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/RD pulse width
/WR pulse width
Access cycle recovery time
Address setup time before /RD or /WR goes low
Address hold time after /RD or /WR high
Data setup time before /WR high
Data valid time after /RD low
Data hold time after /RD high
Data hold time after /WR high
/CS low to /RD or /WR low
0
10
55
12
6
0
0
0
tDHW
tCRWL
tRWCH
/RD or /WR high to /CS high
Figure 10: TD242LP bus cycle timing parameters
TransDimension, Inc.
8
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