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TDOTG242-000C 参数 Datasheet PDF下载

TDOTG242-000C图片预览
型号: TDOTG242-000C
PDF下载: 下载PDF文件 查看货源
内容描述: [Bus Controller, PQFP64,]
分类和应用:
文件页数/大小: 21 页 / 479 K
品牌: PLX [ PLX TECHNOLOGY ]
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TransDimension Inc.  
Interfacing TD242LP to Intel StrongArm SA1110 Processor  
The SA1110’s GPIO control registers should be initialized as follows:  
Register  
GPDR  
GFER  
Register Full Name  
GPIO Pin Direction Register  
GPIO Falling-Edge Detect Register  
GPIO Alternate Function Register  
Bit 14  
Meaning  
input  
enable  
gpio  
Default  
0
1
0
0
undefined  
0
GAFR  
Figure 16: SA1110 GPIO register settings to support TD242LP interrupt  
To enable interrupt, the SA1110 interrupt control registers should be set as follows:  
Register  
ICLR  
ICMR  
Register Full Name  
Interrupt Controller Level Register  
Interrupt Controller Mask Register  
Bit 14  
Meaning  
IRQ  
Enable  
Default  
undefined  
undefined  
0
1
Figure 17: SA1110 interrupt control register settings to support TD242LP interrupt  
In addition, if the user application requires the SA1110 be brought out of the idle mode upon an  
interrupt from the TD242LP, Bit 0 of the SA1110 register ICCR (Interrupt Controller Control  
Register) should be set accordingly.  
Please note that the interrupt generated by the TD242LP is level sensitive. Caution must be taken  
when it is interfaced with an interrupt controller, such as the one in the SA1110, that supports  
only edge-sensitive interrupt sources. In this case, a one more check of interrupt status register  
may be necessary right before getting out of the ISR (the Interrupt Service Routine), which will  
prevent from missing any interrupt.  
Interrupt: TD242LP Configuration  
The software must configure the TD242LP before the SA1110 enables the interrupt originated  
from it. The following steps must be carried out:  
Step 1: Configure the TD242LP INT pin to be active low. This requires Bit 16 of the TD242LP  
Hardware Mode Register (000H) be set to 0, which is the default.  
Step 2: Configure the TD242LP INT pin to be totem-pole output. This requires Bit 21 of the  
IOConfiguration2 Register (04CH) to be set to 1 by user software. Note that the INT pin  
defaults to wired OR output, which should also work if a pull-up resistor is present.  
Step 3: Enable interrupt sources on the TD242LP side, which involves four sets of registers as  
described in detail in Section 4 of the TD242LP Technical Manual.  
USB System Initialization  
It should be emphasized that all SA1110 register settings and the TD242LP hardware system  
settings discussed above must be completed before the USB controllers within the TD242LP are  
activated.  
TransDimension, Inc.  
11  
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