TransDimension Inc.
Interfacing TD242LP to Intel StrongArm SA1110 Processor
tCRWL
tRPW
tACR
CS
tRWCH
RD
A12:A1
valid address
tAHH
tASL
D15:D0
valid data
tDHR
tDVR
Figure 11: TD242LP memory/register read cycle
tACR
tCRWL
tWPW
CS
tRWCH
WR
A12:A1
D15:D0
valid address
tASL
tAHH
valid data
tDSW
tDHW
Figure 12: TD242LP memory/register write cycle
SA1110 Chip Select Programming
Based on the TD242LP register read/write cycle specification, the most significant 16 bits of the
SA1110 register MSC2 (for nCS5) may be programmed according to the following:
Field
RT5
RBW5
RDF5
Bits
Function
Settings
01
Meaning
“SRAM”
16-bit
68 ns
29 ns
Default
undefined
undefined
undefined
undefined
undefined
17:16 Memory type
18
23:19 Access strobe (/RD, /WR) width
32 bit or 16 bit access
1
00110
00010
010
RDN5 28:24 Time between access beats within a burst*
RRR5 31:29 Time between two bursts
* This parameter (RDN5) has no effect for non-burst access.
38 ns
Figure 13: SA1110 register MSC2 setting for TD242LP accessing via nCS5
Bits 31:16 of the SA1110 register MSC2, when initialized to 4235H as shown in the above table,
yield non-burst bus cycles depicted in Figure 14, satisfying the TD242LP timing requirements for
all register accesses.
TransDimension, Inc.
9
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