February, 2007
PCI Express Configuration, Control, and Status Registers
5.3
PCI Express Configuration, Control, and Status
Registers
The PCI Express Configuration, Control, and Status registers that can be initialized are discussed in the
following sections. However, this is not a complete list of programmable registers. For a complete list,
refer to Chapter 11, “PEX 8532 Transparent Mode Port Registers,” and Appendix A, “Serial EEPROM
Memory Map.”
• Section 5.3.1, “Selecting Configuration Values Using Serial EEPROM”
• Section 5.3.2, “Selecting Upstream Port Using Serial EEPROM”
• Section 5.3.3, “Setting Port Configuration Using Serial EEPROM”
• Section 5.3.4, “Power Management Parameters Using Serial EEPROM”
• Section 5.3.5, “Message Signaled Interrupt Capability Using Serial EEPROM”
• Section 5.3.6, “PCI Express Capability Using Serial EEPROM”
• Section 5.3.7, “Device Serial Number Extended Capability Using Serial EEPROM”
• Section 5.3.8, “Power Budgeting Extended Capability Using Serial EEPROM”
• Section 5.3.9, “Virtual Channel Extended Capability Using Serial EEPROM”
• Section 5.3.10, “Advanced Error Reporting Capability Using Serial EEPROM”
The Device-Specific registers cannot be accessed by Configuration requests; however, software can
access these registers with Memory requests.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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