February, 2007
PLX-Specific Registers
5.3.11
PLX-Specific Registers
The following registers are unique to the PEX 8532 device, and are not referenced in PCI Express
documentation. The PLX-Specific registers are organized into the following sections:
• Section 11.13.1, “Error Checking and Debug Registers”
• Section 11.13.2, “Physical Layer Registers”
• Section 11.13.3, “CAM Routing Registers”
• Section 11.13.4, “Ingress Control Registers”
• Section 11.13.5, “I/O CAM Base and Limit Upper 16 Bits Registers”
• Section 11.13.6, “Base Address Registers (BARs)”
• Section 11.13.7, “Shadow Virtual Channel (VC) Capability Registers”
• Section 11.13.8, “Ingress Credit Handler (INCH) Registers”
• Section 11.13.9, “Ingress One-Bit ECC Error Count Register”
• Section 11.13.10, “Relaxed Completion Ordering (Ingress) Register – Silicon Revisions BA/BB/
BC Only”
• Section 11.13.11, “Relaxed Ordering Mode (Ingress) Register”
• Section 11.13.12, “Internal Credit Handler (ITCH) VC&T Threshold Registers”
The Device-Specific registers cannot be accessed by Configuration requests; however, software can
access these registers with Memory requests.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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