February, 2007
Serial EEPROM Initialization
5.2.3
Serial EEPROM Initialization
Note: For further details, refer to the PEX 85XX EEPROM – PEX 8532/8524/8516 Design Note.
The on-chip Serial EEPROM Controller is integrated in PEX 8532 Station 0, as illustrated in Figure 5-2.
The Controller performs a serial EEPROM download when a serial EEPROM is present, as indicated by
the EE_PR# Strapping ball = Low, and when one of the following events occur:
• PEX_PERST# is returned High, following a Fundamental Reset (such as, a Cold or Warm Reset)
• Hot Reset is received at the upstream port (downloading upon this event can be
optionally disabled), by setting the Port 0 register at offset 1DCh[16, 17, and/or 20]
• Upstream port exits a DL_Down condition (downloading upon this event can be
optionally disabled), by setting the Port 0 register at offset 1DCh[16, 17, and/or 20]
Figure 5-2. PEX 8532 Serial EEPROM Connections
PEX 8532
EE_CS#
Station 1
Station 0
EE_DI
Serial
EEPROM
Controller
Initialization
Serial
EE_DO
EEPROM
EE_SK
Configuration Data
EE_PR#
Port 1
Port 2
Port 3
Port 8
Port 9
Port 10 Port 11
Port 0
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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