February, 2007
Secondary Bus Reset
5.1.3.2
Hot Reset Disable
The PEX 8532 includes a configuration option – Debug Control register Upstream Port Hot Reset and
Link Down Reset Propagation Disable bit (Port 0, offset 1DCh[20]) – to ignore the Hot Reset sequence
from the upstream PCI Express link. Setting this bit enables the upstream port to ignore a Hot Reset
training sequence, blocks the switch from manifesting an internal reset due a DL_Down event, and
prevents the downstream ports from issuing a Hot Reset to downstream devices when either a Hot Reset
or DL_Down event occurs on the upstream link.
5.1.4
Secondary Bus Reset
When the upstream PCI-to-PCI bridge Bridge Control register (BCR) Secondary Bus Reset bit
(offset 3Ch[22]) is set to 1, all ports that are downstream from that port are reset to their initial/default
states. The downstream ports propagate an in-band Hot Reset to their respective downstream links. In
addition, the downstream ports’ Configuration Space registers (CSRs) are re-initialized. The upstream
PCI-to-PCI bridge (upstream port) and its CSRs are not affected; however, the queues to/from
all downstream ports are drained, because their upstream-to-downstream virtual connections
are re-initialized.
When the downstream PCI-to-PCI bridge BCR Secondary Bus Reset bit is set to 1, a Hot Reset is
transmitted to its single downstream port, which resets all devices downstream from that port to their
initial/default states. The reset port drops any incoming traffic. All other PEX 8532 traffic not flowing to
the reset port is unaffected.
The downstream links are held in reset until software removes the condition by clearing the BCR
Secondary Bus Reset bit. The PHY layer of the downstream port in question propagates the reset
condition in-band to its downstream link, and remains in the Hot Reset state until the reset condition
(BCR) is cleared. The Transaction Layer draining of non-empty queues to/from the affected port(s) is
handled in a manner similar to the case of that port proceeding to the DL_Inactive state, as defined in the
PCI Express Base r1.0a, Section 2.9.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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