Reset and Initialization
PLX Technology, Inc.
5.2
Initialization Procedure
Upon exit from a Fundamental Reset, the PEX 8532 initialization process is started. There are two or
three steps in the process, depending on the availability of an external initialization serial EEPROM.
The initialization sequence executed is as follows:
1. PEX 8532 reads the Strapping signal balls to determine System mode, upstream port, and lane
configuration of all ports.
2. If the serial EEPROM is present (EE_PR# ball is Low), serial EEPROM data is downloaded to the
PEX 8532 Configuration registers. The configuration from the Strapping signal balls can be changed
by serial EEPROM data.
3. After the configuration from the Strapping signal balls and/or serial EEPROM completes, the
Physical Layer of the configured ports attempts to bring up the links. After both components on a
link enter the initial Link Training state, they proceed through Physical Layer Link initialization and
then through Flow Control initialization for VC0, preparing the Data Link and Transaction Layers to
use the link. Following Flow Control initialization for VC0, it is possible for VC0 Transaction Layer
Packets (TLPs) and Data Link Layer Packets (DLLPs) to be transmitted across the link.
5.2.1
5.2.2
Default Port Configuration
The default upstream port selection and overall port lane-width configuration is determined by
Strapping signal ball levels. All Strapping balls must be tied High to VDD33 or Low to VSS (GND),
which sets the default device configuration. (Refer to Section 3.4.4, “Strapping Signals.”) Some of these
settings can be changed by downloading serial EEPROM data, or through initial port negotiation.
Default Register Initialization
Each PEX 8532 port defined in the Port Configuration process has a set of assigned registers that control
port activities and status during normal operation. These registers are set to default/initial settings, as
defined in:
• Chapter 11, “PEX 8532 Transparent Mode Port Registers”
• Chapter 15, “NT Port Virtual Interface Registers”
• Chapter 16, “NT Port Link Interface Registers”
Following a Fundamental Reset, the basic PCI Express Support registers are initially set to the values
specified in the PCI Express Base r1.0a. The PLX-Specific registers are set to the values specified in
their register description tables. These registers can be changed by loading new data with the attached
serial EEPROM, or by way of Transaction Layer Configuration Space register (CSR) accesses using
Configuration or Memory Writes; however, registers identified as Read-Only (RO) cannot be modified
by Configuration nor Memory Write requests.
The PEX 8532 supports three mechanisms for accessing registers by way of the Transaction Layer,
as described in the following sections:
• Section 11.4.1, “PCI r2.3-Compatible Configuration Mechanism”
• Section 11.4.2, “PCI Express Enhanced Configuration Mechanism”
• Section 11.4.3, “PLX-Specific Memory-Mapped Configuration Mechanism”
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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