Reset and Initialization
PLX Technology, Inc.
5.2.3.1
Configuration Data Download
Serial data is downloaded from the serial EEPROM and converted to parallel data, which is then routed
to the PEX 8532 ports. The Serial EEPROM Controller generates a 7.8-MHz EE_SK signal and reads a
total of 3,044 DWords from the serial EEPROM, which represents the data necessary to initialize the
PEX 8532 registers.
The serial EEPROM Memory map reflects the basic PEX 8532 register map, for registers discussed in
the following chapters:
• Chapter 11, “PEX 8532 Transparent Mode Port Registers”
• Chapter 15, “NT Port Virtual Interface Registers”
• Chapter 16, “NT Port Link Interface Registers”
Because these registers are duplicated for each port, the serial EEPROM data starts with Station 0,
Port 0, offset 00h, and progresses through the registers for all eight ports, in sequence. Certain general
device registers are appended at the end of the space for Port 0, and various Address spaces are skipped
due to unused/reserved register space. A detailed description of the serial EEPROM Memory map is
provided in Appendix A.
While downloading the data, the PEX 8532 generates a CRC value from the Read data. When the serial
EEPROM download is complete, the generated CRC value is compared to a CRC value stored in the last
DWord location of the serial EEPROM. If the CRC values match, the PEX 8532 sets the Serial
EEPROM Status register Serial EEPROM Present field (Port 0, offset 260h[17:16]) to 01b (serial
EEPROM download complete and serial EEPROM CRC is validated).
If the CRC fails:
• The Serial EEPROM Status register Serial EEPROM Present field is set to 11b to indicate
that the serial EEPROM is present but a CRC error was detected, and,
• If the Serial EEPROM Status register CRC Disable bit (Port 0, offset 260h[21]) value is 0
(default), all registers that are serial EEPROM-programmable are reset/initialized to default
values, or,
• If the Serial EEPROM Status register CRC Disable bit value is 1, the CRC error is ignored
and all registers that are serial EEPROM-programmable are initialized with the values that
were downloaded from the serial EEPROM.
Caution:
Setting the CRC Disable bit is strongly discouraged because a corrupted
serial EEPROM download could render the PEX 8532 inoperable until
a Fundamental Reset is applied (by asserting PEX_PERST# input).
During the serial EEPROM download, the Class Code 060400h is monitored. If the correct code is not
found, the download is terminated.
Note: It is the system software’s responsibility to verify whether the serial EEPROM download
completes without error.
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
