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PEX8532-BB25BI 参数 Datasheet PDF下载

PEX8532-BB25BI图片预览
型号: PEX8532-BB25BI
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PBGA680, 35 X 35 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-680]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 512 页 / 4374 K
品牌: PLX [ PLX TECHNOLOGY ]
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Reset and Initialization  
PLX Technology, Inc.  
5.1.3  
Hot Reset  
A Hot Reset is equivalent to a traditional Software Reset. Triggered by an in-band signal from an  
upstream PCI Express link to all downstream ports, a Hot Reset causes all ports that are downstream  
from the initiating port to set their registers and state machines to initial values. This type of reset does  
not require power cycling, nor does it cause PEX 8532 port re-configuration. However, a Hot Reset:  
Causes all TLPs held in the PEX 8532 to be dropped  
Returns all State machines to their initial (default) values  
Returns all Non-Sticky register bits to their initial (default) conditions (refer to Table 11-3,  
“Register Types, Grouped by User Accessibility,” for further details regarding Sticky register  
bit types)  
A Hot Reset is triggered by the following actions:  
Physical Layer (at the upstream port) receives a reset through a training sequence leading  
to a Hot Reset  
Upstream PCI Express port enters the DL_Inactive state, which has the same effect as a Hot Reset  
Note: In the following sections, the terms “virtual PCI-to-PCI bridge” and “port”  
refer to a given Station port.  
5.1.3.1  
Hot Reset Propagation  
Reset is propagated to a downstream PCI Express device through the PCI Express link, using the  
Physical Layer Hot Reset mechanism (that is, a Reset bit in the Training Sequence Ordered-Set from the  
upstream device is set).  
PCI Express views a switch as a hierarchy of virtual PCI-to-PCI bridges.  
An example of reset propagation across the PEX 8532 switch is illustrated in Figure 5-1. Upon  
receiving a Hot Reset from the upstream PCI Express link, the virtual primary PCI-to-PCI bridge  
propagates the reset to virtual secondary PCI-to-PCI bridges in the upstream and downstream ports.  
Each virtual secondary PCI-to-PCI bridge propagates the reset to its downstream links, and initializes its  
internal states to initial/default conditions.  
A Hot Reset does not impact Clock Logic, Port Configuration, nor Sticky register bits.  
Figure 5-1. PEX 8532 System Reset Propagation Example  
Reset  
Propagation  
Upstream  
Port  
Upstream  
P-P Bridge  
P-P  
Downstream  
P-P Bridges  
P-P  
P-P  
P-P  
P-P  
P-P  
P-P  
P-P  
Downstream  
Ports  
Upstream Station  
Downstream Station  
70  
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book  
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6  
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