Functional Overview
PLX Technology, Inc.
Transaction Layer Receive/Ingress Protocol
The ingress side Transaction Layer collects and stores inbound TLP traffic in Virtual Channel buffers.
The incoming data is checked for ECRC errors, valid Type field, length matching the Header Transfer
Size field, and other TLP-specific errors defined by the PCI Express Base r1.0a.
Header and Data Payload are forwarded to the Source Scheduler, to be routed to the switch
outgoing port.
Transaction Layer Transmit/Egress Protocol
The egress side Transaction Layer receives information from other switch ports and generates outbound
requests and completion TLPs, which it stores in Virtual Channel buffers. This layer assembles
Transaction Layer packets, which consist of identification Headers, Data Payloads, and ECRC. Details
for these fields are defined in the PCI Express Base r1.0a, Section 2.2.
The PEX 8532 implements an egress Flow Control (FC) protocol that ensures it does not transmit a TLP
over a link to a remote receiver unless the receiving device contains sufficient Virtual Channel (VC)
buffer space to accommodate the packet. This flow control is automatically managed by the hardware
and is transparent to software. Software is used only to enable additional buffers, to supplement the
initial default buffer assignment.
4.3.1.4
4.3.1.5
Virtual Channels and Traffic Classes
The PEX 8532 supports two Virtual Channels – VC0 and VC1 – and up to eight Traffic Classes –
TC[7:0]). VC0 and TC0 are required by the PCI Express Base r1.0a, and configured at device start-up.
The second Virtual Channel (VC1) is enabled by the PEX 8532 default configuration procedure, but can
be disabled by using serial EEPROM configuration to clear the Port VC Capability 1 register Extended
VC Count bit (offset 14Ch[0]).
Non-Blocking Crossbar Switch Architecture
The non-blocking Crossbar Switch is an on-chip interconnect switch-fabric module (internal fabric)
used to link multiple stations. The physical topology of the Crossbar Switch interconnect is a packet
beat-based internal fabric designed to simultaneously connect multiple on-chip logic stations.
The Crossbar Switch protocol is sufficiently flexible and robust to support a variety of embedded system
needs. The protocol is specifically designed to ease chip integration by strongly enforcing station
boundaries and standardizing communication between stations.
The Crossbar Switch architecture incorporates the following functions:
• Multiple concurrent data transfers with maximum throughput
• Global ordering within the switch
• Internal credit guarantees packet forward progress once scheduled
• Deadlock avoidance
• Priority preemption
• Two independent Virtual Channels (VC0 and VC1)
• PCI Express Ordering rules
• Packet fair queuing
• Oldest first scheduling
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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