February, 2007
Relaxed Ordering
4.3.2
Relaxed Ordering
The PEX 8532 does not support the optional Relaxed Ordering capability defined in the
PCI Express Base r1.0a. However, is does support two PLX-Specific Relaxed Ordering modes:
• PEX 8532 Relaxed Ordering
• PEX 8532 Relaxed Completion Ordering – Silicon Revisions BA/BB/BC Only
4.3.2.1
PEX 8532 Relaxed Ordering
The PEX 8532 does not support the TLP optional Relaxed Ordering bit, as specified in the
PCI Express Base r1.0a, Table 2-23. By default, all packets entering from a specific port are dispatched
to their respective destinations, based on strict ordering.
However, to remove unnecessary head-of-line blocking caused by PCI ordering in applications where
ordering is not important, the PEX 8532 offers a PLX-Specific Relaxed Ordering mode. PLX-Specific
Relaxed Ordering mode is enabled when any bit within a PLX-Specific Relaxed Ordering Mode
register Enable PLX Relaxed Ordering field is set to 1:
• Port 0 or 8 – offset BFCh[7:0]
• Port 1 or 9 – offset BFCh[15:8]
• Port 2 or 10 – offset BFCh[23:16]
• Port 3 or 11 – offset BFCh[31:24]
In general, each port has 8 TCs to which it can map.
The ingress scheduler on a specific port (for a specific Traffic Class) selects packets without using
ordering requirements and dispatches the packets to the egress ports. If using the Relaxed Ordering
feature, ensure that it is used only for packets of a specific Traffic Class. This allows those packets to be
distinguished from packets on other Traffic Classes in which the Relaxed Ordering feature is
not enabled.
After the packets reach the egress ports, strict ordering is used in these queues, irrespective of the bits set
on the ingress port.
Refer to Section 8.3.2.3, “PLX-Specific Relaxed Ordering,” for further details.
4.3.2.2
PEX 8532 Relaxed Completion Ordering –
Silicon Revisions BA/BB/BC Only
The PEX 8532 provides a Relaxed Completion Ordering feature that enables Completion transactions to
pass enqueued Posted transactions that are blocked. This feature is available on VC0, and is enabled by
setting the following bits in the Device-Specific Configuration space:
• PLX-Specific Relaxed Ordering Enable register PLX-Specific Relaxed Ordering Enable bit
(Ports 0, 1, 2, 3, 8, 9, 10, and/or 11, offset 1F0h[20]) is set to 1, and
• PLX-Specific Relaxed Completion Ordering (Ingress) register Enable PLX-Specific Relaxed
Completion Ordering bit (Port 0 or 8, offset BECh[0]) is set to 1, and
• Any bit within a PLX-Specific Relaxed Ordering Mode register Enable PLX Relaxed Ordering
field is set to 1
– Port 0 or 8 – offset BFCh[7:0]
– Port 1 or 9 – offset BFCh[15:8]
– Port 2 or 10 – offset BFCh[23:16]
– Port 3 or 11 – offset BFCh[31:24]
In general, each port has 8 TCs to which it can map.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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