February, 2007
PEX 8532 Functional Blocks
4.3.1.1
Physical Layer
The Physical Layer module interfaces to the PCI Express lanes and implements the PHY Layer
functions. The number of ports per station can vary from one to four, with a cumulative lane-bandwidth
of x16. When there are fewer than four configured/enabled ports, the x16 bandwidth can be shared by
the remaining active ports, as defined in Table 4-1. PHY Layer functions include:
• Establishing port configurations and SerDes-to-port assignments
• Establishing internal bandwidth division among ports
• Supporting cross-linked upstream and downstream ports
• 8b/10b encoding/decoding
• Data scrambling/unscrambling
• Packet framing
• Loop-Back Master and Slave support
• Pseudo-Random Bit Sequence (PRBS) data generation and checking
• User-defined test pattern with SKIP Ordered-Set insertion and return data checking
• Driver and Input buffers
• Parallel-to-serial and serial-to-parallel conversion
• PLLs and Clock circuitry
• Impedance-matching circuitry
• Interface initialization and maintenance functions
Physical Layer Command and Status Registers
The Physical Layer operating conditions are defined in Section 11.13.2, “Physical Layer Registers.”
The system host can track the link operating status and re-configure link parameters, by way of
these registers.
Hardware Link Interface Configuration
The PEX 8532 Physical Layer of each station can include up to four integrated quad Serializer/
De-serializer (SerDes) modules, which provide the PCI Express hardware interface lanes. The SerDes
modules provide all physical communication controls and functions required by the
PCI Express Base r1.0a. SerDes modules are clustered into ports, to provide the links that connect to
other PCI Express devices.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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