Functional Overview
PLX Technology, Inc.
4.3.1.2
Data Link Layer
The Data Link Layer (DLL) serves as an intermediate stage between the Transaction Layer and the
Physical Layer. The primary responsibility of the Data Link Layer includes link management and data
integrity, including error detection and correction.
The transmission side of the Data Link Layer accepts Transaction Layer Packets (TLPs) assembled by
the Transaction Layer, calculates and applies data protection code and TLP Sequence Number, and
submits them to the Physical Layer for transmission across the link.
The receiving Data Link Layer is responsible for checking the integrity of received TLPs and submitting
them to the Transaction Layer for further processing. On detection of TLP error(s), this Layer is
responsible for requesting re-transmission of TLPs until the information is correctly received, or the link
is determined to have failed.
Data Link Layer Packet (DLLP)
The Data Link Layer also generates and consumes packets used for Link management functions.
To differentiate these packets from the TLPs used by the Transaction Layer, the term Data Link Layer
Packet (DLLP) is used when referring to packets generated and consumed at the Data Link Layer. The
rules governing the identification and formation of these packets are defined in the
PCI Express Base r1.0a, Section 3.4.1.
FC Credits
The initial number of flow control credits advertised for Virtual Channel 0 is listed in Section 8.4.2.1,
“Ingress Side.” The flow control credits are also programmable through the serial EEPROM. The
Transaction Layer must schedule an Update FC DLLP for transmission, to replenish the number of
advertised credits or to meet an updated VC Timer. When enabled, the Transaction Layer initiates flow
credit initialization for VC1, following VC0 initialization.
Packet Arbiter
The Packet Arbiter determines what type of packet to forward to the PHY layer, on a per port basis. The
priority algorithm implemented by the Packet Arbiter is discussed in Section 8.4.5.1, “Arbitration
between DLLP and TLP,” and follows the recommended priority provided in the
PCI Express Base r1.0a, Section 3.5.2.1.
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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