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PEX8532-BB25BI 参数 Datasheet PDF下载

PEX8532-BB25BI图片预览
型号: PEX8532-BB25BI
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PBGA680, 35 X 35 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-680]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 512 页 / 4374 K
品牌: PLX [ PLX TECHNOLOGY ]
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February, 2007  
Intelligent Adapter Mode  
4.4.1  
Intelligent Adapter Mode  
The use of Non-Transparent bridges in PCI systems is well established for supporting intelligent  
adapters in enterprise and multi-host systems. The same concept is used in PCI Express bridges  
and switches.  
In Figure 4-7, there are two Type 0 CSR headers in the Non-Transparent PCI-to-PCI bridge. The one  
nearer the internal virtual bus is referred to as the Virtual Interface. The one nearer the PCI Express link  
is referred to as the Link Interface.  
In Intelligent Adapter mode, the NT Port Link Interface is connected to the System domain. The System  
Host manages only the NT Port Link Interface Type 0 function. The Local Host manages all PEX 8532  
Transparent Port Type 1 and NT Port Virtual Interface Type 0 functions. Cross-domain traffic is routed  
through an Address Translation mechanism. (Refer to Section 12.1.6, “Address Translation.”)  
After power-up, the PEX 8532 Non-Transparent Type 1 ports, including the NT Port Virtual Interface,  
are enumerated by the Local Host connected to the PEX 8532 upstream port. The Local Host enables  
and resizes the Base Address registers (BARs) by programming the NT Port Link Interface BAR  
Setup/Limit registers, before the System Host assigns resources for these BARs. This behavior is  
changed with serial EEPROM initialization.  
After the Local Host finishes its enumeration, it enables the NT Port Link Interface to be enumerated by  
the System Host connected to the interface. The NT Port Link Interface Retries the System Host  
Configuration transaction until the Local Host enables the NT Port Link Interface to process the System  
Host Configuration transaction. The Debug Control register Virtual Interface Access Enable bit  
(offset 1DCh[28]) enables access to the Virtual Interface Configuration registers. The Link Interface  
Access Enable bit (offset 1DCh[29]) enables access to the Link Interface Configuration registers.  
These bits do not affect normal Memory, Memory-Mapped CSRs, nor I/O-Mapped CSR transactions.  
Intelligent Adapter mode does not support Host-Failover applications.  
Figure 4-7. PEX 8532 Intelligent Adapter Software Model  
Fabric/  
System Host  
Local Host  
I/O Fabric  
Non-Transparent  
Upstream Port  
PEX 8532  
Transparent  
Upstream Port  
Link Interface  
Primary  
Transparent  
Upstream  
P-P Bridge  
P-P Bridge  
CSR / BAR  
CSR  
BAR  
Non-Transparent  
Downstream  
P-P Bridge  
Address Translation  
CSR / BAR  
Virtual Interface  
Transparent  
Downstream  
P-P Bridges  
P-P  
P-P  
P-P  
Transparent  
Downstream Ports  
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book  
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6  
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