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PEX8532-BB25BI 参数 Datasheet PDF下载

PEX8532-BB25BI图片预览
型号: PEX8532-BB25BI
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PBGA680, 35 X 35 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-680]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 512 页 / 4374 K
品牌: PLX [ PLX TECHNOLOGY ]
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Functional Overview  
PLX Technology, Inc.  
4.2.2  
Interrupts  
Generated interrupts are INTx Interrupt message-type (compatible with the PCI r2.3-defined Interrupt  
signals) or Message Signaled Interrupts (MSI), when enabled. MSI and INTx are mutually exclusive;  
either can be enabled in a system (depending on which interrupt type the system software supports), but  
never both. [Refer to the Message Signaled Interrupt Capability register (offset 48h) and Command  
register Interrupt Disable bit (offset 04h[10]).] The PEX 8532 does not convert received INTx messages  
to MSI messages.  
Refer to Chapter 6, “Interrupts,” for complete details.  
4.2.2.1  
4.2.2.2  
Interrupt Sources or Events  
The PEX 8532-generated interrupt/message sources include:  
Hot Plug events  
Device-specific error events  
INTx  
INTx Switch Mapping  
The PEX 8532 remaps and collapses the INTx virtual wires, based on downstream port Device Number  
and received INTx message Requester ID Device Number. Each virtual PCI-to-PCI bridge  
of a downstream port specifies the Port Number associated with the INTx (Interrupt) messages received  
or generated, and forwards the interrupt messages in the upstream direction. Refer to Section 6.2.1,  
“INTx-Type Interrupt Message Remapping and Collapsing,” for interrupt routing information.  
58  
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book  
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6  
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