February, 2007
System Reset
4.2.1
System Reset
The PEX 8532 can be reset by four different mechanisms (refer to Section 5.1, “Reset Overview,”
for details):
• Fundamental Reset input, through the PEX_PERST# signal
• In-band Reset propagates from upstream, through the Physical Layer mechanism, which
communicates a reset through a training sequence (TS1/TS2 Ordered-Set Hot Reset or
Disable Link bit is set)
• PCI Express link enters the DL_Down state on the upstream port
• Upstream port Bridge Control register Secondary Bus Reset bit is set (offset 3Ch[22]=1)
Reset is propagated from upstream to downstream. Reset is propagated to the downstream PCI Express
device, through the PCI Express link by the Physical Layer mechanism (the TS1/TS2 Ordered-Set
Hot Reset bit is set), or when the upstream port link enters the DL_Down state. (Refer to Section 5.1,
“Reset Overview,” for further details.)
An example of reset propagation is illustrated in Figure 4-5. Upon receiving a reset from the upstream
PCI Express link, the upstream port PCI-to-PCI bridge propagates the reset to the downstream port
PCI-to-PCI bridges in the upstream station, as well as to the downstream port PCI-to-PCI bridges in its
downstream station.
Figure 4-5. PEX 8532 System Reset Propagation
Reset
Propagation
Upstream
Port
Upstream
P-P Bridge
P-P
Downstream
P-P Bridges
P-P
P-P
P-P
P-P
P-P
P-P
P-P
Downstream
Ports
Upstream Station
Downstream Station
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
57
PLX [ PLX TECHNOLOGY ]
