February, 2007
Configuration Header Registers
Register 11-16. 3Ch Bridge Control and Interrupt Signal (All Ports) (Cont.)
Serial
EEPROM
Bit(s)
Description
Type
Default
VGA 16-Bit Decode
Silicon Revision AA
Not supported
RW
No
0
Cleared to 0.
Silicon Revisions BA/BB/BC
Enables the PEX 8532 to provide 16-bit decoding of the VGA I/O address,
precluding the decoding of alias addresses every 1 KB. Useful only when
bit 19 (VGA Enable) of this register is also set to 1, enabling VGA I/O
decoding and bridge forwarding.
20
Enables system configuration software to select between 10- and 16-bit
I/O address decoding for all VGA I/O register accesses that are
forwarded from the primary to secondary interface, when the
VGA Enable bit is set to 1.
RW
Yes
0
0 = Execute 10-bit address decodes on VGA I/O accesses
1 = Execute 16-bit address decodes on VGA I/O accesses
Master Abort Mode
21
22
RO
No
0
0
Cleared to 0, as required by the PCI Express Base r1.0a.
Secondary Bus Reset
RW
Yes
1 = Causes a Hot Reset on the corresponding PEX 8532 port secondary/
downstream PCI Bus
Fast Back-to-Back Transactions Enable
23
24
25
26
27
RO
RO
RO
RO
RO
No
No
No
No
No
0
0
0
0
Cleared to 0, as required by the PCI Express Base r1.0a.
Primary Discard Timer
Cleared to 0, as required by the PCI Express Base r1.0a.
Secondary Discard Timer
Cleared to 0, as required by the PCI Express Base r1.0a.
Discard Timer Status
Cleared to 0, as required by the PCI Express Base r1.0a.
Discard Timer SERR# Enable
0
Cleared to 0, as required by the PCI Express Base r1.0a.
31:28 Reserved
0h
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
167
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