February, 2007
Configuration Header Registers
Register 11-10. 24h Prefetchable Memory Base and Limit Address (All Ports)
Serial
EEPROM
Bit(s)
Description
Type
Default
Prefetchable Memory Base Address
Prefetchable Memory Base Capability
1h = Corresponding PEX 8532 port defaults to 64-bit Prefetchable Memory
Addressing support
3:0
RO
Yes
Yes
1h
Note: If the application needs 32-bit only Prefetchable space, the
serial EEPROM must not equal the value of this field and bits [19:16]
(Prefetchable Memory Limit Address register Prefetchable Memory
Limit Capability field).
Prefetchable Memory Base Address[31:20]
Specifies the corresponding PEX 8532 port Prefetchable Memory Base
Address[31:20].
15:4
RW
FFFh
The PEX 8532 assumes Prefetchable Memory Base Address[19:0]=00000h.
Prefetchable Memory Limit Address
Prefetchable Memory Limit Capability
19:16
31:20
RO
Yes
Yes
1h
1h = Corresponding PEX 8532 port defaults to 64-bit Prefetchable Memory
Addressing support
Prefetchable Memory Limit Address[31:20]
Specifies the corresponding PEX 8532 port Prefetchable Memory Base
Address[31:20].
RW
000h
The PEX 8532 assumes Prefetchable Memory Base Address[19:0]=FFFFFh.
Note: The PEX 8532 port forwards Memory transactions from its primary interface to its secondary interface
(downstream) if a Memory address is within the range defined by the Prefetchable Memory Base
(offsets 28h + 24h[15:0]) and Prefetchable Memory Limit (offsets 2Ch + 24h[31:16]) registers
(when the Base is less than or equal to the Limit).
Conversely, the PEX 8532 port forwards Memory transactions from its secondary interface to its primary
interface (upstream) if a Memory address is outside this Address range [provided the address is not within
the range defined by the Memory Base Address and Memory Limit Address registers (offset 20h).
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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