PEX 8532 Transparent Mode Port Registers
PLX Technology, Inc.
Register 11-11. 28h Prefetchable Memory Upper Base Address[63:32] (All Ports)
Serial
EEPROM
Bit(s)
Description
Type
Default
Prefetchable Memory Base Address[63:32]
Silicon Revision AA
The PEX 8532 uses this register for Prefetchable Memory Upper Base
Address[63:32].
RW
Yes
FFFF_FFFFh
31:0
Silicon Revisions BA/BB/BC
RW
Yes
0000_0000h
The PEX 8532 uses this register for Prefetchable Memory Upper Base
Address[63:32].
Register 11-12. 2Ch Prefetchable Memory Upper Limit Address[63:32] (All Ports)
Serial
EEPROM
Bit(s)
Description
Type
Default
Prefetchable Memory Limit Address[63:32]
31:0
RW
Yes
0000_0000h
The PEX 8532 uses this register for Prefetchable Memory Upper Limit
Address[63:32].
Register 11-13. 30h I/O Base Address[31:16] and I/O Limit Address[31:16] (All Ports)
Serial
EEPROM
Bit(s)
Description
Type
Default
I/O Base Upper 16 Bits
15:0
RW
Yes
Yes
FFFFh
The PEX 8532 uses this register for I/O Base Address[31:16].
I/O Limit Upper 16 Bits
31:16
RW
0000h
The PEX 8532 uses this register for I/O Limit Address[31:16].
Register 11-14. 34h Capabilities Pointer (All Ports)
Serial
EEPROM
Bit(s)
Description
Type
Default
Capability Pointer
7:0
RO
Yes
40h
Default 40h points to the Power Management Capability register.
31:8
Reserved
0000_00h
Register 11-15. 38h Expansion ROM Base Address (All Ports)
Serial
EEPROM
Bit(s)
Description
Expansion ROM Base Address
Type
Default
31:0
RO
No
0000_0000h
Not supported
Cleared to 0000_0000h.
164
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
