February, 2007
Configuration Header Registers
Register 11-8. 1Ch Secondary Status, I/O Limit, and I/O Base (All Ports) (Cont.)
Serial
EEPROM
Bit(s)
Description
Secondary Status
Type
Default
20:16 Reserved
0-0h
66 MHz Capable
Not supported
0 = Not enabled, as PCI Express does not support 66 MHz
21
22
23
RO
RO
No
No
0
0
0
Reserved
Fast Back-to-Back Transactions Capable
Not supported
0 = Not enabled, as PCI Express does not support this function
Master Data Parity Error
If the Parity Error Response Enable bit value is 1, the corresponding PEX 8532
port sets this bit to 1 when it transmits or receives a TLP on its downstream side,
and when either of the following two conditions occur:
24
RW1C
RO
Yes
No
0
•
•
Port receives Completion marked poisoned
Port forwards poisoned TLP write request
If the Parity Error Response Enable bit = 0, the PEX 8532 never sets this bit.
DEVSEL Timing
26:25
00b
Cleared to 00b, as required by the PCI Express Base r1.0a.
29:27 Reserved
Received System Error
000b
30
RW1C
RW1C
Yes
Yes
0
0
Set to 1 when a port receives an ERR_FATAL or ERR_NONFATAL message on
its secondary interface.
Detected Parity Error
Set to 1 by the secondary side of a Type 1 Configuration Space Header device
when the device receives a poisoned TLP, regardless of the Parity Error Response
Enable bit state.
31
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
161
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