PEX 8532 Transparent Mode Port Registers
PLX Technology, Inc.
Register 11-9. 20h Memory Base and Limit Address (All Ports)
Serial
Default
Bit(s)
Description
Memory Base Address
Type
EEPROM
3:0
Reserved
0h
Memory Base Address[31:20]
15:4
RW
Yes
FFFh
Specifies the corresponding PEX 8532 port Memory Base Address[31:20].
The PEX 8532 assumes Memory Base Address[19:0]=00000h.
Memory Limit Address
19:16 Reserved
Memory Limit Address[31:20]
0h
Specifies the corresponding PEX 8532 port Non-Prefetchable Memory Limit
Address[31:20].
31:20
RW
Yes
000h
The PEX 8532 assumes Memory Limit Address[19:0]=FFFFFh.
Note: The PEX 8532 port forwards Memory transactions from its primary interface to its secondary interface
(downstream) if a Memory address is within the range defined by the Memory Base Address and
Memory Limit Address registers (when the Base is less than or equal to the Limit).
Conversely, the PEX 8532 port forwards Memory transactions from its secondary interface to its primary
interface (upstream) if a Memory address is outside this Address range [provided the address is not within
the range defined by the Prefetchable Memory Base (offsets 28h + 24h[15:0]) and Prefetchable Memory
Limit (offsets 2Ch + 24h[31:16])] registers.
162
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
