PEX 8532 Transparent Mode Port Registers
PLX Technology, Inc.
Register 11-5. 10h Base Address 0 (Upstream Port Only; Reserved for Downstream Ports)
Serial
EEPROM
Bit(s)
Description
Memory Space Indicator
Ports
Type
Default
When enabled, the Base Address register maps the
corresponding PEX 8532 port Configuration registers into
Memory space.
Upstream
RO
No
0
0
0
Note: Hardwired to 0.
Reserved for downstream ports.
Memory Map Type
Downstream
00b = Corresponding PEX 8532 port Configuration registers
can be mapped anywhere in 32-bit Memory Address space
10b = Corresponding PEX 8532 port Configuration registers
can be mapped anywhere in 64-bit Memory Address space
01b, 11b = Reserved
Reserved for downstream ports.
Prefetchable
Upstream
RO
RO
RW
Yes
No
00b
2:1
Downstream
Upstream
00b
0
The Base Address register maps the corresponding
PEX 8532 port Configuration registers into
Non-Prefetchable Memory space by default.
3
Note: Hardwired to 0.
Reserved for downstream ports.
Reserved
Downstream
0
16:4
No
0-0h
Base Address
Upstream
Yes
0000h
0000h
Base Address for PLX-Specific Memory-Mapped
Configuration mechanism.
31:17
Reserved for downstream ports.
Downstream
Register 11-6. 14h Base Address 1 (Upstream Port Only; Reserved for Downstream Ports)
Serial
EEPROM
Bit(s)
Description
Ports
Type
Default
Base Address 1
For 64-bit addressing (Base Address 0 register
Memory Map Type field is set to 10b), Base Address
1 extends Base Address 0 to provide the upper
32 Address bits.
RW
Yes
Upstream
0000_0000h
0000_0000h
31:0
Read-Only when the Base Address 0 register
Memory Map Type field indicates 32-bit memory
addressing (offset 10h[2:1]=00b).
RO
No
Reserved for downstream ports.
Downstream
158
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
