February, 2007
Configuration Header Registers
Register 11-4. 0Ch Miscellaneous Control (All Ports)
Serial
EEPROM
Bit(s)
Description
Type
Default
Cache Line Size
7:0
RW
Yes
00h
Implemented as a Read-Write field for Conventional PCI-compatibility
purposes and does not impact PEX 8532 functionality.
Primary Latency Timer
15:8
RO
RO
No
00h
01h
Cleared to 00h, as required by the PCI Express Base r1.0a.
Header Type
Corresponding PEX 8532 port Configuration Space header adheres to
the Type 1 PCI-to-PCI Bridge Configuration Space layout defined by
the PCI-to-PCI Bridge r1.1.
22:16
Yes
Multi-Function
23
RO
RO
Yes
No
0
Always 0, because the PEX 8532 is a single-function device.
BIST
31:24
00h
Not supported
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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