PEX 8532 Transparent Mode Port Registers
PLX Technology, Inc.
Register 11-2. 04h Command/Status (All Ports)
Serial
Default
Bit(s)
Description
Type
EEPROM
Command
I/O Access Enable
0 = PEX 8532 ignores I/O accesses on the corresponding port’s primary
interface
1 = PEX 8532 responds to I/O accesses on the corresponding port’s primary
interface
0
RW
Yes
Yes
0
0
Memory Access Enable
0 = PEX 8532 ignores Memory accesses on the corresponding port’s primary
interface
1 = PEX 8532 responds to Memory accesses on the corresponding port’s
primary interface
1
2
RW
RW
Bus Master Enable
Controls the PEX 8532 Memory and I/O request forwarding in the upstream
direction. Neither affect message forwarding nor Completions in the upstream
or downstream direction.
0 = PEX 8532 handles Memory and I/O requests received on the corresponding
port downstream/secondary interface as Unsupported Requests (UR);
for Non-Posted Requests, the PEX 8532 returns a Completion with
UR Completion status
Yes
0
1 = PEX 8532 forwards Memory and I/O requests in the upstream direction
Special Cycle Enable
3
4
5
6
7
RO
RO
RO
RW
RO
No
No
No
Yes
No
0
0
0
0
0
Cleared to 0, as required by the PCI Express Base r1.0a.
Memory Write and Invalidate
Cleared to 0, as required by the PCI Express Base r1.0a.
VGA Palette Snoop
Cleared to 0, as required by the PCI Express Base r1.0a.
Parity Error Response Enable
Controls the Master Data Parity Error bit.
IDSEL Stepping/Wait Cycle Control
Cleared to 0, as required by the PCI Express Base r1.0a.
SERR# Enable
8
9
RW
RO
Yes
No
0
0
Controls the Signaled System Error bit. When = 1, enables reporting of Fatal and
Non-Fatal errors detected by the device to the Root Complex.
Fast Back-to-Back Transactions Enabled
Cleared to 0, as required by the PCI Express Base r1.0a.
Interrupt Disable
0 = Corresponding PEX 8532 port is enabled to generate INTx Interrupt
messages
10
RW
Yes
0
1 = Corresponding PEX 8532 port is prevented from generating INTx Interrupt
messages
15:11 Reserved
00h
154
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
