February, 2007
Configuration Header Registers
Register 11-2. 04h Command/Status (All Ports) (Cont.)
Serial
EEPROM
Bit(s)
Description
Type
Default
Status
18:16 Reserved
000b
0
Interrupt Status
0 = No INTx Interrupt message is pending
1 = INTx Interrupt message is pending internally to the corresponding
19
20
RO
Yes
PEX 8532 port
Capabilities List
RO
RO
Yes
No
1
Required by the PCI Express Base r1.0a to be 1 at all times.
66 MHz Capable
21
22
23
0
0
0
Cleared to 0, as required by the PCI Express Base r1.0a.
Reserved
Fast Back-to-Back Transactions Capable
RO
No
Cleared to 0, as required by the PCI Express Base r1.0a.
Master Data Parity Error
If the Parity Error Response Enable bit is set to 1, the corresponding PEX 8532
port sets this bit to 1 when the port:
•
Forwards the poisoned TLP Write request from the secondary to the
primary interface, or
•
Receives a Completion marked as poisoned on the primary interface
24
RW1C
Yes
0
If the Parity Error Response Enable bit is cleared to 0, the PEX 8532 never sets
this bit.
This error is natively reported by the Uncorrectable Error Status register
Poisoned TLP Status bit (offset FB8h[12]), which is mapped to this bit for
Conventional PCI backward compatibility.
DEVSEL Timing
26:25
27
RO
No
00b
0
Cleared to 00b, as required by the PCI Express Base r1.0a.
Signaled Target Abort
When a Memory-Mapped access payload length is greater than one DWord,
the PEX 8532 upstream port sets this bit to 1.
This error is natively reported by the Uncorrectable Error Status register
Completer Abort Status bit (offset FB8h[15]), which is mapped to this bit
for Conventional PCI backward compatibility.
RW1C
Yes
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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