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PEX8532-BB25BI 参数 Datasheet PDF下载

PEX8532-BB25BI图片预览
型号: PEX8532-BB25BI
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PBGA680, 35 X 35 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-680]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 512 页 / 4374 K
品牌: PLX [ PLX TECHNOLOGY ]
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PEX 8532 Transparent Mode Port Registers  
PLX Technology, Inc.  
Register 11-2. 04h Command/Status (All Ports) (Cont.)  
Serial  
Default  
Bit(s)  
Description  
Type  
EEPROM  
Received Target Abort  
28  
RO  
No  
No  
0
0
Cleared to 0. It is never set to 1.  
Received Master Abort  
29  
RO  
Cleared to 0. It is never set to 1.  
Signaled System Error  
When the SERR# Enable bit is set to 1, the corresponding PEX 8532 port  
sets this bit to 1 when it transmits an ERR_FATAL or ERR_NONFATAL  
message to its upstream device.  
This error is natively reported by the Device Status register Fatal Error Detected  
and Non-Fatal Error Detected bits (offset 70h[18:17], respectively), which are  
mapped to this bit for Conventional PCI backward compatibility.  
30  
RW1C  
Yes  
Yes  
0
0
Detected Parity Error  
Set to 1 when the corresponding port receives a Poisoned TLP on its primary  
side, regardless of the Parity Error Response Enable bit state.  
This error is natively reported by the upstream port’s Uncorrectable Error  
Status register Poisoned TLP Status bit (offset FB8h[12]), which is mapped  
to this bit for Conventional PCI backward compatibility.  
31  
RW1C  
Register 11-3. 08h Class Code and Revision ID (All Ports)  
Serial  
EEPROM  
Bit(s)  
Description  
Type  
Default  
Revision ID  
Unless overwritten by the serial EEPROM, returns the silicon revision (AAh,  
BAh, BBh, or BCh), the PLX-assigned Revision ID for this version of the  
PEX 8532. The PEX 8532 Serial EEPROM register initialization capability  
is used to replace the PLX Revision ID with another Revision ID.  
AAh,  
BAh,  
Yes  
(Refer  
to Note)  
7:0  
RO  
BBh,  
Note: Silicon Revision BB only – Bit 0 is hardwired to 1 and is not  
programmable by serial EEPROM.  
or BCh  
Silicon Revision BC only – Bits [2:0] are hardwired to 100b and are not  
programmable by serial EEPROM.  
Class Code  
060400h  
Programming Interface  
15:8  
RO  
Yes  
00h  
PEX 8532 ports support the PCI-to-PCI Bridge r1.1 requirements, but not  
subtractive decoding, on its upstream interface.  
Sub-Class Code  
23:16  
31:24  
RO  
RO  
Yes  
Yes  
04h  
06h  
PCI-to-PCI bridge.  
Base Class Code  
Bridge device.  
156  
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book  
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6  
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