February, 2007
Configuration Header Registers
11.6
Configuration Header Registers
Table 11-4. Configuration Header Register Map (All Ports)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Vendor ID
Command
Device ID
Status
00h
04h
08h
Class Code
Revision ID
Header Type and
BIST (Not Supported)
Primary Latency Timer
Cache Line Size
0Ch
Multi-Function
Base Address 0
Base Address 1
Subordinate Bus Number Secondary Bus Number
Secondary Status I/O Limit
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
Secondary Latency Timer
Primary Bus Number
I/O Base
Memory Limit Address
Memory Base Address
Prefetchable Memory Base Address
Prefetchable Memory Limit Address
Prefetchable Memory Upper Base Address[63:32]
Prefetchable Memory Upper Limit Address[63:32]
I/O Limit Upper 16 Bits I/O Base Upper 16 Bits
Reserved
Capability Pointer (40h)
Expansion ROM Base Address (Not Supported)
Bridge Control
Interrupt Pin
Interrupt Line
Register 11-1. 00h Product Identification (All Ports)
Serial
EEPROM
Bit(s)
Description
Type
Default
Vendor ID
Unless overwritten by the serial EEPROM, returns the PLX
PCI-SIG-assigned Vendor ID. The PEX 8532 Serial EEPROM
register initialization capability is used to replace the PLX
Vendor ID with another Vendor ID.
15:0
HwInit
Yes
Yes
10B5h
Device ID
Unless overwritten by the serial EEPROM, 8532h is returned
by the PEX 8532, the PLX-assigned Device ID. The Serial
EEPROM register initialization capability is used to replace
the PLX-assigned Device ID with another Device ID.
31:16
HwInit
8532h
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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