PEX 8532 Transparent Mode Port Registers
PLX Technology, Inc.
11.5
Register Descriptions
The remainder of this chapter details the PEX 8532 registers, including:
• Bit/field names
• Description of register functions for the PEX 8532 upstream port and downstream ports
• Type (such as RW or HwInit; refer to Table 11-3 for Type descriptions)
• Whether the power-on/reset value can be modified by way of the PEX 8532 serial EEPROM
initialization feature
• Default power-on/reset value
Table 11-3. Register Types, Grouped by User Accessibility
Type
Description
Hardware Initialized
Refers to the PEX 8532 Hardware Initialization mechanism or PEX 8532 Serial
EEPROM register initialization feature. Read-Only after initialization and can only
be reset with a Fundamental Reset.
HwInit
Read-Write
RW
Read/Write and is set or cleared to the needed state by software.
Read-Only Status, Write 1 to Clear
RW1C
RW1CS
Write 1 to clear status register or bit. Indicates status when read. A status bit set by the
system to 1 (to indicate status) is cleared by writing 1 to that bit. Writing 0 has no effect.
Read-Only Status, Write 1 to Clear, Sticky
Same as RW1C, except that bits are not modified by a Hot Reset.
Read-Write, Write 1 to Set, Sticky
Non-Transparent ports contain these types of Device-Specific Control registers.
Software writes 1 to the register to enable control and 1 to a register with
RW1C privilege to clear the control. Writing 0 has no effect.
RW1S
Read-Write, Sticky
Same as RW, except that bits are not modified by a Hot Reset.
RWS
RO
Read-Only
Read-Only and cannot be altered by software. Initialized by the PEX 8532 hardware
initialization mechanism or PEX 8532 serial EEPROM register initialization feature.
Read-Only, Sticky
Same as RO, except that bits are not initialized nor modified by a Hot Reset.
ROS
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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