PEX 8532 Transparent Mode Port Registers
PLX Technology, Inc.
11.4
Register Access
Each PEX 8532 port implements a 4-KB Configuration space. The lower 256 bytes (offsets 00h through
FFh) is the PCI-compatible Configuration space, and the upper 960 Dwords (offsets 100h through
FFFh) is the PCI Express Extended Configuration space. The PEX 8532 supports three mechanisms for
accessing registers:
• PCI r2.3-Compatible Configuration Mechanism
• PCI Express Enhanced Configuration Mechanism
• PLX-Specific Memory-Mapped Configuration Mechanism
11.4.1
PCI r2.3-Compatible Configuration Mechanism
The PCI r2.3-Compatible Configuration mechanism provides standard access to the PEX 8532 ports’
first 256 bytes (the bytes at offsets 00h through FFh) of the PCI Express Configuration space.
This mechanism is used to access the PEX 8532 port Type 1 (PCI-to-PCI Bridge) registers:
• Configuration Header Registers
• Power Management Capability Registers
• Message Signaled Interrupt Capability Registers
• PCI Express Capability Registers
The PCI r2.3-Compatible Configuration mechanism uses PCI Type 0 and Type 1 Configuration
transactions to access the PEX 8532 Configuration registers. The PEX 8532 upstream port captures the
Bus and Device Numbers assigned by the upstream device on the PCI Express link attached to the
PEX 8532 upstream port, as required by the PCI Express Base r1.0a.
The PEX 8532 decodes all Type 1 Configuration accesses received on its upstream port, when any of the
following conditions exist:
• If the Bus Number specified in the Configuration access is the number of the PEX 8532 internal
Virtual PCI Bus, the PEX 8532 automatically converts the Type 1 Configuration access into the
appropriate Type 0 Configuration access for the specified device.
– If the specified device corresponds to the PCI-to-PCI bridge in one of the PEX 8532
downstream ports, the PEX 8532 processes the Read or Write request to the specified
downstream port register specified in the original Type 1 Configuration access.
– If the specified Device Number does not correspond to any of the PEX 8532 downstream
port Device Numbers, the PEX 8532 responds with an Unsupported Request (UR).
• If the specified Bus Number in the Type 1 Configuration access is not the number
of the PEX 8532 internal virtual PCI Bus, but is the number of one of the PEX 8532
downstream port secondary/subordinate buses, the PEX 8532 passes the configuration
access onto the PCI Express link attached to that PEX 8532 downstream port.
• If the specified Bus Number is the downstream port Secondary Bus Number, and the
specified Device Number is 0, the PEX 8532 converts the Type 1 Configuration access
to a Type 0 Configuration access before passing it on.
• If the specified Device Number is not 0, the downstream port drops the TLP and
generates a UR.
• If the specified Bus Number is not the downstream port Secondary Bus Number,
the PEX 8532 passes along the Type 1 Configuration access, without change.
148
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
