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PEX8532-BB25BI 参数 Datasheet PDF下载

PEX8532-BB25BI图片预览
型号: PEX8532-BB25BI
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PBGA680, 35 X 35 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-680]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 512 页 / 4374 K
品牌: PLX [ PLX TECHNOLOGY ]
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Power Management  
PLX Technology, Inc.  
Table 10-2. Supported PCI Express Power Management Capabilities (Cont.)  
Register  
Supported  
Description  
Offset  
Bit(s)  
Yes  
No  
Device Status and Control  
Auxiliary (AUX) Power PM Enable  
10  
20  
70h  
Cleared to 0 for each port.  
Auxiliary (AUX) Power Detected  
Cleared to 0 for each port.  
Link Capabilities  
Active State Power Management (ASPM) Support  
Indicates the level of ASPM supported by the port.  
01b = L0s link power state entry is supported  
10b = L0s and L1 link power states are supported  
All other values are reserved.  
11:10  
74h  
L0s Exit Latency  
14:12  
17:15  
101b = Corresponding PEX 8532 port L0s Exit Latency is between 1 and 2 µs  
L1 Exit Latency  
101b = Corresponding PEX 8532 port L1 Exit Latency is between 16 and 32 µs  
Link Status and Control  
Active State Power Management (ASPM) Control  
00b = Disables L0s and L1 Entries for the corresponding PEX 8532 portc  
01b = Enables only L0s Entry  
78h  
1:0  
10b = Enables only L1 Entry  
11b = Enables both L0s and L1 Entries  
Slot Capabilities (for Downstream Ports)  
Attention Button Present  
0 = Attention Button is not implemented  
0
1
2
3
1 = Attention Button is implemented on the slot chassis of the corresponding  
PEX 8532 downstream port  
Do not change for upstream port.  
Power Controller Present  
0 = Power Controller is not implemented  
1 = Power Controller is implemented for the slot of the corresponding PEX 8532  
downstream port  
7Ch  
Do not change for upstream port.  
MRL Sensor Present  
0 = MRL Sensor is not implemented  
1 = MRL Sensor is implemented on the slot chassis of the corresponding PEX 8532  
downstream port  
Do not change for upstream port.  
Attention Indicator Present  
0 = Attention Indicator is not implemented  
1 = Attention Indicator is implemented on the slot chassis of the corresponding  
PEX 8532 downstream port  
Do not change for upstream port.  
c. The port receiver must be capable of entering the L0s state, regardless of whether the state is disabled.  
140  
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book  
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6  
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