February, 2007
PEX 8532 PCI Express Power Management Support
10.1.3
PEX 8532 PCI Express Power Management Support
The PEX 8532 supports PCI Express features that are required or important for PCI Express switch
Power Management. Table 10-2 lists supported and non-supported features and the register bits/fields
used for configuration or activation.
Table 10-2. Supported PCI Express Power Management Capabilities
Register
Supported
Description
Offset
Bit(s)
Yes
No
Power Management Capability
Capability ID
7:0
✔
Set to 01h, indicating that the data structure currently being pointed to is the
PCI Power Management data structure.
Next Capability Pointer
✔
✔
✔
15:8
18:16
19
Default 48h points to the Message Signaled Interrupt Capability register.
Version
Default 010b indicates compliance with the PCI Power Mgmt. r1.1.
PME Clock
Cleared to 0, as required by the PCI Express Base r1.0a.
Device-Specific Initialization
40h
✔
✔
21
Default 0 indicates that Device-Specific Initialization is not required.
AUX Current
24:22
Default 000b indicates that the PEX 8532 does not support Auxiliary Current
requirements.
D1 Support
✔
✔
25
26
Default 0 indicates that the PEX 8532 does not support the D1 power state.
D2 Support
Default 0 indicates that the PEX 8532 does not support the D2 power state.
PME Support
✔
31:27
Default 11001b indicates that the corresponding PEX 8532 port forwards
PME messages in the D0, D3hot, and D3cold power states.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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