Power Management
PLX Technology, Inc.
Table 10-2. Supported PCI Express Power Management Capabilities (Cont.)
Register
Supported
Description
Offset
Bit(s)
Yes
No
Power Budget Capability
144h
System Allocated
✔
0
1 = Power budget for the device is included within the system power budget
Power Management Hot Plug User Configuration
L0s Entry Idle Count
Time to meet to enter L0s.
0 = Idle condition lasts for 1 µs
1 = Idle condition lasts for 4 µs
✔
0
L1 Upstream Port Receiver Idle Count
For active L1 entry.
0 = Upstream port receiver idle for 2 µs
1 = Upstream port receiver idle for 3 µs
✔
✔
1
2
HPC PME Turn-Off Enable
1 = PME Turn-off message is transmitted before the port is turned Off on
a downstream port
HPC T
Delay
1E0h
pepv
Slot power-applied to power-valid delay time.
00b = 16 ms
01b = 32 ms
10b = 64 ms
11b = 128 ms
✔
4:3
HPC Inband Presence-Detect Enable
0 = HP_PRSNT[3:0]# or HP_PRSNT[11:8]# Input balls are used to detect a board
present in the slot
1 = SerDes receiver detect mechanism is used to detect a board present in the slot
5
6
✔
✔
HPC T
Delay
pvperl
Downstream port power-valid to reset signal release time.
0 = 20 ms
1 = 100 ms (default)
144
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
