Power Management
PLX Technology, Inc.
10.1.2
Link Power Management State
The Power Management state of a link is determined by the D-state of its downstream link. The
PEX 8532 holds its upstream and downstream links in the L0 state when it is in standard operating mode
(PCI PM state in D0_active). Active-State Link Power Management defines a protocol for components
in the D0 state, to reduce link power by placing their links into a low-power state and instructs the
opposite end of the link to do likewise. This capability allows Hardware-Autonomous, dynamic-link
power reduction beyond what is achievable by Software-Only Power Management. Table 10-1 defines
the relationship between a PEX 8532 power state and its downstream link.
Table 10-1. Power States of Connected Link Components
Downstream
Component D State
PEX 8532
D State
Permissible
Interconnect State
Power Saving Actions
L0
Full power.
D0
D0
L0s, L1 (optional)
PHY Transmit lanes in high-impedance state.
D1
D2
D0
D0
L1
L1
PHY Transmit lanes in high-impedance state.
PHY Transmit lanes in high-impedance state.
FC and DLL ACK/NAK timers suspended.
PLL can be disabled.
D3hot
D0 or D3hota
L1, L2/L3 Ready
D0, D3hot, or
D3cold
D3cold (no AUX Power)
L3
Link-Off State. No power to component.
a. The PEX 8532 initiates a link-state transition of its upstream port to L1 when the port is programmed to D3hot.
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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